Low Power VLSI Design by Walter de Gruyter

Author:Walter de Gruyter
Language: eng
Format: epub
Publisher: Walter de Gruyter
Published: 2016-04-17T04:00:00+00:00

Figure 4.73: Output waveforms of first 8 nodes of 16-bit CLA based on Energy Efficient Adiabatic Logic (EEAL).

Table 4.14 shows the power dissipation for varying bit length for different types of multiplier circuits. The performance of multipliers is crucial for multimedia applications such as 3-D graphics and signal processing systems, which depend on the execution of large numbers of multiplications. Hence a Vedic Multiplier, based on UrdhvaTiryakbhyam Sutra (UTS) of Vedic Arithmetic, a promising approach due to less computational time, has also been given [21]. The multiplier is based on UTS of ancient Vedic Mathematics. The aim of this work is to demonstrate the advantages of concurrent generation and addition of partial products in Vedic Multiplier. It can be classified as a serial-parallel multiplier, which serves as a good trade-off between the time-consuming serial multipliers and area-consuming parallel multipliers.

UrdhvaTiryakbhyam Sutra: UrdhvaTiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. It literally means “Vertically and Crosswise”. Let us explain UTS with an example. The numbers to be multiplied are written on two consecutive sides of the square as shown in Figure 4.74. The square is divided into rows and columns where each row/column corresponds to one of the digits of either a multiplier or a multiplicand. These small boxes are partitioned into two halves by the crosswise lines. Block diagram of the Vedic Multiplier is given in Figure 4.74. The schematics are given in Figures 4.75–4.77. The output waveform is shown in Fig. 4.78.

Table 4.14: Power dissipation of multiplier circuits with varying bit lengths at 100 MHz for 180 nm CMOS technology.

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